1. Field of the Invention
The present invention relates to electrically programmable, non-volatile, read-only memory and integrated circuits including such memory, and more particularly to a memory cell structure and method of operation based upon charge trapping structures adapted for E-field assisted tunneling.
2. Description of Related Art
Electrically programmable non-volatile memory technologies are being adapted to many applications. The various technologies vary in the number of times that the memory cells can be programmed, the voltages required to achieve programming, and the number of bits of data stored in each memory cell. Also, an important consideration in determining whether to apply a particular memory technology is the manufacturing steps required to form the memory cells and supporting circuitry.
Memory technologies also vary according to the array architecture. One popular architecture is known as the NAND-type array. NAND arrays for flash memory use small cells, and operate at high speeds. However, as design rules have scaled down toward 70 nanometers, and below, floating gate type NAND flash memory becomes impractical due to poor endurance, and parasitic capacitance between adjacent floating gates which deteriorates the cell threshold voltage distribution. On the other hand, the so-called SONOS type NAND flash memory has been explored, which is based on charge trapping silicon-oxide-nitride-oxide-silicon (SONOS) memory cells. The SONOS type NAND array is free of these technology issues below the design rule of 70 nm. The SONOS NAND flash memory is configured for programming by direct tunneling, requiring a tunnel oxide less than 30 nanometers thick for silicon dioxide based dielectrics. However, poor data retention and slow erase speed remain roadblocks for the application of the SONOS cell for high density NAND flash memory. SONOS-type cells have also been applied in the so-called NROM configuration, which employs hot-electron tunneling for programming, and hot hole injection for erase. The NROM cell has a very thick bottom oxide (greater than 70 Angstroms silicon dioxide equivalent thickness) in order to achieve acceptable data retention and endurance.
It is desirable to provide electrically programmable non-volatile memory cell technologies that can be implemented with very high density, and achieve long data retention, and can be made using processes more compatible with standard CMOS logic manufacturing techniques.